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There was a problem with saving your item s for later. A number of chip cooling methods, which include passive and active cooling methods, have been proposed. Passive methods include thermal conduction pastes, metal lines, and vias , natural convection finned heat sinks and ventilation slots , radiation coatings and paints , heat pipes, and thermosyphons [ 5 ]. These passive devices are easily designed and generally inexpensive to implement, but typically perform worse than active-cooling devices.

Active cooling requires input power, which requires external components such as forced convection devices fans and nozzles , pumped loops heat exchangers and cold plates , and refrigerators Peltier thermoelectric and vapor-compression-based [ 5 ]. However, these cooling methods cannot be embedded in 3D IC structures with a small enough size or effective cooling, and are still unable to address the varying thermal profiles of an IC. Microfluidics, also called lab-on-a-chip, is the science and technology of systems that process or manipulate small amounts of fluids, using channels or flat platforms with dimensions of tens to hundreds of micrometers [ 6 ].

System on a chip

In , American Business 2. Moreover, most research works focus on applications in biology, chemistry, materials science, and medical science. More recently, microfluidics cooling has been demonstrated as promising for 3D ICs with high power density. Since , the U. There are 85 publications available concerning 3D ICs with microfluidics. Five dissertations and 80 journal or conference publications have been presented on basic principles and methods.

These research works can be summarized into six categories: cooling structure design, co-design issues, through silicon via TSV influence, specific chip application, thermal models, and non-uniform heating and hotspots. Section 2 focuses on cooling structure design.


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  • Section 3 describes co-design issues in microfluidic cooling for 3D ICs. Section 4 shows how the design of TSVs in microfludic cooling can be optimized. Section 5 focuses on microfluidic cooling for specific chip applications. Section 6 presents thermal models, characteristics, and transmissions.

    The Next Generation of System-on-Chip Integration, 1st Edition

    Section 7 focuses on non-uniform heating and hotspots. The last section summarizes the review and concludes. Micropores and microchannels are directly fabricated into intra-chips [ 12 ]. The interchip approach uses the microgap as a cooling channel between chips in three-dimensional stacks [ 13 , 14 ]. Based on the conceptual model of the ICECool program, several different structures of microfluidic cooling embedded into 3D ICs have been presented.

    Yue Zhang et al. The tier-specific cooling approach, compared with conventional microfluidic cooling, can reduce the pumping power by The tier-specific microfluidic cooling technology in 3D stacks. Reproduced with permission from [ 15 ]. In Figure 3 , the blue arrows indicate cold coolants and red arrows indicate hot coolants. To develop the structure in Figure 3 , Minhaj Hassan et al.

    Experimental results certified that conventional air cooling solutions limit 3D stacks [ 16 ]. To solve stack bonding, Yassir Madhour et al.

    Integrated Circuits & Systems

    The method was developed and successfully tested [ 17 ]. Paragkumar et al. Modified microfluidic cooling structures, shown in Figure 4 , have also been studied. Each chip had its own fluidic inlet and outlet. Flow direction and flow rate were modified independently for each die based on individual demands [ 19 , 20 , 21 ].

    This approach achieved independent cooling for each tier and can be used for different temperature distributions and velocities. A 3D system with independent microfluidic cooling. Reproduced with permission from [ 21 ].

    Typical processes are shown in Figure 5. The processes started with the deposition of silicon dioxide followed by metal depositing. A thin chrome layer was chosen as an etch mask, as shown in Figure 5 b. Using the chrome mask, the silicon dioxide layer was etched, and using a CR-7S chrome etchant, the remaining chrome was removed. Figure 5 c shows the resulting silicon dioxide as an etch mask. The high-aspect-ratio Bosch process etched via holes through the silicon wafer.

    Systems on a Chip (SOCs) as Fast As Possible

    Figure 5 d shows that the wet oxidation isolates the vias from the silicon substrate. Titanium and copper seed layers were deposited using an e-beam evaporator at the backside of the wafer. Moreover, chemical mechanical polishing will need to be removed the overburden Figure 5 e. A micropin-fin heat sink structure, shown in Figure 5 f, will then be achieved. A new strategy integrates the computational, electrical, physical, thermal, and reliability aspects of a system.

    System on a chip - Wikipedia

    The unification of these diverse aspects of ICs is called co-design. The independent optimization and design of each aspect leads to sub-optimal designs considering the lack of understanding of cross-domain interactions and their impacts on the feasibility region of the architectural design space. Thus co-design enables optimization with efficient design and high-performance configurations.

    Although the co-design strategy is becoming increasingly imperative in IC design, 3D ICs with efficient microfluidic cooling has become even more critical. The interlayer coupling with cooling structures, and a higher degree of connectivity between components, exacerbates the interdependence between physical design parameters, architectural parameters, and a multitude of metrics of interest such as performance, hotspot distribution, power, and reliability.

    The embedded microfluidic cooling greatly influences the former parameters. Co-design becomes critical in 3D ICs with microfluidic cooling. Jianyong Xie et al. The finite-volume formulations of heat equations and the voltage distribution equation for both solid medium and fluid flow are carefully explained. Based on the proposed iterative co-simulation method, package voltage dropped and temperature distribution with fluidic cooling effects can be estimated [ 22 ].

    Zhimin Wan et al. The simulator executed benchmark programs to create power traces that drive thermal analysis. After using a compact thermal model, thermal characteristics under liquid cooling were investigated, and four alternative packaging organizations were compared. With a given pumping power, the greatest overall temperature reduction was reached, with two pin-fin-enhanced microgaps and two tiers, where the high power dissipation tier is on the top. At last, the pin-fin parameters were optimized such that significant improvements in energy instruction were made, and leakage power, as well as the height, the diameter, and the longitudinal and transversal spacing, significantly decreased [ 23 ].

    Bing Shi et al. The thermal TSVs acted as heat removal agents and as beneficial heat conduction paths to the micro-channel structures. Caleb Serafy presented a scheme for multi-domain co-optimization and co-simulation of 3D central processing unit CPU architectures with both microfluidic and air cooling solutions, and demonstrated a paradigm for design space modeling and exploration in the co-design scheme, and discussed possible avenues for improvement of this work in the future [ 25 ]. The thickness of chips or of gaps between chips has been modified to embed microfluidic cooling structures into 3D stacks.

    The coolant and structure will result in a change in electrical characterization including high frequency. The impact of microfluidic cooling on the electrical characteristics of ICs has been studied.